DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 531

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.8.6
Transmission: Before making the transition to module stop, software standby, or subsleep mode,
stop all operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the
output pins during each mode depend on the port settings, and the pins output a high-level signal
after mode cancellation. If the transition is made during data transmission, the data being
transmitted will be undefined.
To transmit data in the same transmission mode after mode cancellation, set the TE bit to 1, read
SSR, write to TDR, clear TDRE to 0 in this order, and then start transmission. To transmit data in
a different transmission mode, initialize the SCI first.
Figure 16.21 shows a sample flowchart for mode transition during transmission. Figures 16.22
and 16.23 show the pin states during transmission.
Figure 16.21 Sample Flowchart for Mode Transition during Transmission
SCI Operations during Mode Transitions
Make transition to software standby mode etc.
Cancel software standby mode etc.
Change operating mode?
Read TEND flag in SSR
All data transmitted?
<Start transmission>
<Transmission>
Initialization
TEND = 1
Yes
Yes
Yes
TE = 0
[2]
No
No
No
TE = 1
[1]
[3]
[1] Data being transmitted is lost
[2] Clear TIE and TEIE to 0 when
[3] Module stop mode is included.
halfway. Data can be normally
transmitted from the CPU by
setting TE to 1, reading SSR,
writing to TDR, and clearing
TDRE to 0 after mode
cancellation.
they are set to 1.
Rev.2.00 May. 28, 2009 Page 491 of 732
REJ09B0059-0200