DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 488

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3
The SCI has the following registers for each channel.
• Receive shift register (RSR)
• Receive data register (RDR)
• Transmit data register (TDR)
• Transmit shift register (TSR)
• Serial mode register (SMR)
• Serial control register (SCR)
• Serial status register (SSR)
• Serial interface mode register (SCMR)
• Bit rate register (BRR)
16.3.1
RSR is a shift register used to receive serial data that converts it into parallel data. When one
frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly
accessed by the CPU.
16.3.2
RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial
data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR can
receive the next data. Since RSR and RDR function is a double buffer in this way, continuous
receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read
RDR for only once. RDR cannot be written to by the CPU. The initial value of RDR is H'00.
16.3.3
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it
transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered
structure of TDR and TSR enables continuous serial transmission. If the next transmit data has
already been written to TDR when one frame of data is transmitted, the SCI transfers the written
data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at
all times, to achieve reliable serial transmission, write transmit data to TDR for only once after
confirming that the TDRE bit in SSR is set to 1. The initial value of TDR is H'FF.
Rev.2.00 May. 28, 2009 Page 448 of 732
REJ09B0059-0200
Register Descriptions
Receive Shift Register (RSR)
Receive Data Register (RDR)
Transmit Data Register (TDR)