DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 496

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 16.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode. The initial value of BRR is H'FF, and BRR can be read from or
written to by the CPU at all times.
Table 16.2 Relationships between N Setting in BRR and Bit Rate B
Notes: B: Bit rate (bit/s)
Table 16.3 shows sample N settings in BRR in normal asynchronous mode. Table 16.4 shows the
maximum bit rate settable for each operating frequency. Table 16.6 shows sample N settings in
BRR in clocked synchronous mode. Tables 16.5 and 16.7 show the maximum bit rates with
external clock input.
Rev.2.00 May. 28, 2009 Page 456 of 732
REJ09B0059-0200
Mode
Asynchronous mode
Clocked synchronous
mode
Smart card interface
mode
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following table.
CKS1
0
0
1
1
Bit Rate Register (BRR)
SMR Setting
CKS0
0
1
0
1
Bit Rate
B =
B =
B =
64 × 2
8 × 2
S × 2
φ
2n – 1
2n + 1
× 10
φ
2n – 1
φ
× 10
× 10
× (N + 1)
× (N + 1)
× (N + 1)
6
n
0
1
2
3
6
6
BCP1
0
0
1
1
Error
Error (%) = {
⎯
Error (%) =
SMR Setting
{
BCP0
0
1
0
1
B × 64 × 2
B × S × 2
φ
× 10
2n – 1
2n + 1
6
φ
× 10
× (N + 1)
× (N + 1)
6
S
32
64
372
256
– 1 } × 100
–1 × 100
}