DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 21

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 I
17.1 Features .............................................................................................................................497
17.2 Input/Output Pins .............................................................................................................. 500
17.3 Register Descriptions ........................................................................................................500
17.4 Operation...........................................................................................................................514
17.5 Interrupt Requests .............................................................................................................528
17.6 Bit Synchronous Circuit....................................................................................................529
Section 18 A/D Converter................................................................................. 531
18.1 Features .............................................................................................................................531
18.2 Input/Output Pins .............................................................................................................. 533
18.3 Register Descriptions ........................................................................................................534
18.4 Operation...........................................................................................................................538
16.8.6 SCI Operations during Mode Transitions ............................................................491
16.8.7 Switching from SCK Pins to Port Pins ................................................................494
17.3.1 I
17.3.2 I
17.3.3 I
17.3.4 I
17.3.5 I
17.3.6 Slave Address Register (SAR) .............................................................................509
17.3.7 Slave Address Register A (SARA) ......................................................................510
17.3.8 Slave Address Register B (SARB).......................................................................510
17.3.9 Slave Address Mask Register (SAMR)................................................................511
17.3.10 I
17.3.11 I
17.3.12 I
17.3.13 I
17.4.1 I
17.4.2 Master Transmit Operation ..................................................................................515
17.4.3 Master Receive Operation....................................................................................517
17.4.4 Slave Transmit Operation ....................................................................................519
17.4.5 Slave Receive Operation......................................................................................521
17.4.6 Noise Canceler .....................................................................................................523
17.4.7 Example of Use....................................................................................................523
18.3.1 A/D Data Registers A to H (ADDRA to ADDRH)..............................................534
18.3.2 A/D Control/Status Register (ADCSR) ...............................................................535
18.3.3 A/D Control Register (ADCR) ............................................................................537
18.4.1 Single Mode.........................................................................................................538
18.4.2 Scan Mode ...........................................................................................................538
18.4.3 Input Sampling and A/D Conversion Time..........................................................539
2
2
2
2
2
2
2
2
2
2
2
C Bus Control Register A (ICCRA) ..................................................................501
C Bus Control Register B (ICCRB)...................................................................503
C Bus Mode Register (ICMR) ...........................................................................504
C Bus Interrupt Enable Register (ICIER) ..........................................................505
C Bus Status Register (ICSR)............................................................................507
C Bus Status Register A (ICSRA) .....................................................................512
C Bus Transmit Data Register (ICDRT)............................................................512
C Bus Receive Data Register (ICDRR) .............................................................512
C Bus Shift Register (ICDRS) ...........................................................................513
C Bus Format.....................................................................................................514
C Bus Interface 3 (IIC3) ............................................................... 497
Rev.2.00 May. 28, 2009 Page xix of xxxviii
REJ09B0059-0200