DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 699

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.4
22.4.1
In software standby mode, I/O port states are retained. Therefore, there is no reduction in current
consumption for the output current when a high-level signal is output.
22.4.2
Current consumption increases during the oscillation stabilization standby period.
22.4.3
Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module
stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU
interrupt source. Interrupts should therefore be disabled before entering module stop mode.
22.4.4
MSTPCR and EXMSTPCR should only be written to by the CPU.
22.4.5
The following points should be noted in clock division mode.
• Select the clock division ratio specified by the SCK2 to SCK0 bits so that the frequency of φ is
• All the on-chip peripheral modules operate on φ. Therefore, note that the time processing of
• Note that the clock output of the φ pin will be changed by changing the clock division ratio.
within the operation guaranteed range of clock cycle time tcyc shown in the Electrical
Characteristics. In other words, the range of φ must be specified to 5 MHz (min.); outside of
this range (φ < 5 MHz) must be prevented.
modules such as a timer and SCI differs before and after changing the clock division ratio. In
addition, wait time for clearing software standby mode differs by changing the clock division
ratio.
Usage Notes
I/O Port State
Current Consumption during Oscillation Stabilization Standby Period
On-Chip Peripheral Module Interrupts
Writing to MSTPCR, EXMSTPCR
Notes on Clock Division Mode
Rev.2.00 May. 28, 2009 Page 659 of 732
REJ09B0059-0200