DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 170

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.6
When this LSI accesses the external address space, it can insert a 1-state idle cycle (T
bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM with a long output floating time, and
high-speed memory and I/O interfaces.
In the case of normal extended mode if an external write occurs after an external read while the
ICIS bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle.
In the case of multiplex extended mode if an external cycle occurs after an external read while the
ICIS bit is set to 1 in BCR, an idle cycle is inserted at the start of the external cycle after the
external read.
Figure 6.27 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle
for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.27 (a),
with no idle cycle inserted, a conflict occurs in bus cycle B between the read data from ROM and
the CPU write data. In figure 6.27 (b), an idle cycle is inserted, thus preventing data conflict.
Rev.2.00 May. 28, 2009 Page 130 of 732
REJ09B0059-0200
Address bus
Idle Cycle
Data bus
φ
(a) No idle cycle insertion
T
1
Bus cycle A
Long output floating time
Figure 6.27 Examples of Idle Cycle Operation
T
2
T
3
Bus cycle B
T
1
T
2
Data conflict
Address bus
Data bus
φ
T
1
Bus cycle A
T
(b) Idle cycle insertion
2
T
3
T
I
Bus cycle B
T
1
I
) between
T
2