DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 495

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3.8
SCMR is a register that selects the SCI functions.
Bit
7 to 4
3
2
1
0
Serial Interface Mode Register (SCMR)
Bit Name
⎯
SDIR
SINV
⎯
⎯
Initial Value
All 1
0
0
1
0
R/W
R
R/W
R/W
R
R/W
Description
Reserved
These bits are always read as 1 and cannot
be modified.
Data Transfer Direction
Selects the serial/parallel conversion format.
0: TDR contents are transmitted with LSB-
Stores receive data as LSB first in RDR.
1: TDR contents are transmitted with MSB-
Stores receive data as MSB first in RDR.
The SDIR bit is valid only when the 8-bit data
format is used for transmission/reception;
when the 7-bit data format is used, data is
always transmitted/received with LSB-first.
Data Invert
Specifies inversion of the data logic level. The
SINV bit does not affect the logic level of the
parity bit. When the parity bit is inverted, invert
the O/E bit in SMR.
0: TDR contents are transmitted as they are.
1: TDR contents are inverted before being
Reserved
This bit is always read as 1 and cannot be
modified.
Reserved
The initial value should not be changed.
first.
first.
Receive data is stored as it is in RDR.
transmitted. Receive data is stored in
inverted form in RDR.
Rev.2.00 May. 28, 2009 Page 455 of 732
REJ09B0059-0200