DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 389

IC H8S/2437 MCU FLASH 128QFP

DF2437FV

Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of DF2437FV

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2437FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12.5.4
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock at overflow/underflow of TCNT_2 as
set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase counting mode.
Table 12.18 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the
Table 12.18 Cascaded Combinations
Combination
Channels 1 and 2
Example of Cascaded Operation Setting Procedure:
Figure 12.21 shows an example of the setting procedure for cascaded operation.
Examples of Cascaded Operation:
Figure 12.22 illustrates the operation when counting upon TCNT_2 overflow/underflow has been
set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the
TIOC pin rising edge has been selected.
counter operates independently in phase counting mode.
Cascaded Operation
<Cascaded operation>
Cascaded operation
Figure 12.21 Cascaded Operation Setting Procedure
Set cascading
Start counting
Upper 16 Bits
TCNT_1
[1]
[2]
[1]
[2]
Set bits TPSC2 to TPSC0 in the channel 1 TCR
to B'111 to select TCNT_2 overflow/underflow
counting.
Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
Lower 16 Bits
TCNT_2
Rev.2.00 May. 28, 2009 Page 349 of 732
REJ09B0059-0200

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