DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 619

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.4.2
The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be
programmed/erased.)
Programming/erasing is executed by downloading the program in the microcomputer.
The overview of programming/erasing flow is shown in figure 20.9.
High voltage is applied to the internal flash memory during programming/erasing processing.
Therefore, a transition to a reset or hardware standby must not be made during
programming/erasing processing. Doing so may damage or destroy flash memory. If a reset is
executed accidentally, a reset must be released after the reset input period of 100 μs which is
longer than normal.
User Program Mode
program data is prepared
transferred to the on-chip
Programming/erasing
Programming/erasing
When programming,
Programming/erasing
procedure program is
RAM and executed
start
end
Figure 20.9 Overview of Programming/Erasing Flow
1.
2.
3.
4.
Make sure that program data will not overlap the download
destination specified by FTDAR.
The FWE bit is set to 1 by inputting a high level signal to the FWE
pin.
Programming/erasing is executed only in the on-chip RAM.
However, if program data is in a consecutive area and can be
accessed by the MOV.B instruction of the CPU like RAM or
ROM, the program data can be in an external space.
After programming/erasing is finished, input a low level signal to
the FWE pin and enter the hardware protection state.
Rev.2.00 May. 28, 2009 Page 579 of 732
REJ09B0059-0200