DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 621

IC H8S/2437 MCU FLASH 128QFP

DF2437FV

Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of DF2437FV

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2437FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(2) Programming Procedure in User Program Mode
The procedures for download, initialization, and programming are shown in figure 20.11.
The procedure program must be executed in an area other than the flash memory to be
programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be
executed in the on-chip RAM.
The area that can be executed in each step of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 20.4.4, Storable Area for Procedure Program and
Program Data.
The following description assumes the area to be programmed in the user MAT is erased and
program data is prepared in the consecutive area. When erasing is not executed, erasing should be
executed before programming.
JSR FTDAR setting + 32
Select on-chip program
to be downloaded and
destination by FTDAR
procedure program
Set SCO to 1 and
execute download
Start programming
specify download
Set FKEY to H'A5
Set the FPEFEQ
Clear FKEY to 0
DPFR = 0?
Initialization
FPFR = 0?
parameter
1
Yes
Yes
Initialization error processing
Download error processing
No
No
Figure 20.11 Programming Procedure
1.
2.
3.
4.
5.
6.
7.
8.
No
Rev.2.00 May. 28, 2009 Page 581 of 732
JSR FTDAR setting + 16
Disable interrupts and bus
Set parameters to ER1
(FMPAR and FMPDR)
procedure program
End programming
Set FKEY to H'5A
Clear FKEY to 0
master operation
programming is
other than CPU
Programming
Required data
FPFR = 0?
completed?
and ER0
1
Yes
Yes
Clear FKEY and
error processing
No
programming
REJ09B0059-0200
9.
10.
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15.

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