DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 617

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 20.6 System Clock Frequency for Automatic-Bit-Rate Adjustment
(2) State Transition Diagram
The overview of the state transition diagram after boot mode is initiated is shown in figure 20.8.
1. Bit rate adjustment
2. Waiting for inquiry set command
3. Automatic erasure of all user MAT and user boot MAT
4. Waiting for programming/erasing command
• When the program preparation notice is received, the state for waiting program data is entered.
• When the erasure preparation notice is received, the state for waiting erase-block data is
• There are many commands other than programming/erasing: sum check, blank check (erasure
Note that memory read of the user MAT/user boot MAT is only applied to data programmed after
all user MAT/user boot MAT has been automatically erased.
Bit Rate of Host
4,800 bps
9,600 bps
19,200 bps
After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host.
For inquiries about the user-MAT size and configuration, MAT start address, and support state,
the required information is transmitted to the host.
After inquiries have finished, all user MAT and user boot MAT are automatically erased.
The programming start address and program data must be transmitted following the
programming command. When programming is finished, the programming start address must
be set to H'FFFFFFFF and transmitted. Then the state for waiting program data is returned to
the state for waiting programming/erasing command.
entered. The erase-block number must be transmitted following the erasing command. When
the erasure is finished, the erase-block number must be set to H'FF and transmitted. Then the
state for waiting erase-block data is returned to the state for waiting programming/erasing
command. The erasure must be used when the specified block is programmed without a reset
start after programming is executed in boot mode. When programming can be executed by
only one operation, all blocks are erased before the state for waiting
programming/erasing/other command is entered. Thus the erasing operation is not required.
check), and memory read of the user MAT/user boot MAT and acquisition of current status
information.
System Clock Frequency which can Automatically Adjust Bit Rate of
this LSI
5 to 20 MHz
5 to 20 MHz
5 to 20 MHz
Rev.2.00 May. 28, 2009 Page 577 of 732
REJ09B0059-0200