DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 456

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.4.9
Using the signals generated/selected with the timer connection, it is possible to generate an
waveform based on the composite synchronization signal (blanking waveform). This function is
not available in channel 1.
One kind of blanking waveform is generated by combining HFBACKI and VFBACKI inputs,
with the phase polarity made positive by means of bits HFINV and VFINV in TCONRI, and with
the IVO signal.
The logic of CBLANK output waveform generation is shown in figure 13.17.
Rev.2.00 May. 28, 2009 Page 416 of 732
REJ09B0059-0200
Mode
Separate
mode
HFBACKI input (positive)
VFBACKI input (positive)
IVO signal (positive)
CBLANK Output
IVI Signal
VSYNCI
input
Figure 13.17 CBLANK Output Waveform Generation
IVO Signal
IVI signal (without fall
modification or IHI
synchronization)
IVI signal (without fall
modification, with IHI
synchronization)
IVI signal (with fall
modification, without IHI
synchronization)
IVI signal (with fall
modification and IHI
synchronization)
IVG signal
Falling edge sensing
Rising edge sensing
Reset
Set
Meaning of IVO Signal
VSYNCI input (vertical synchronization
signal) is output directly
Meaningless if VSYNCI input (vertical
synchronization signal) is synchronized
with HSYNCI input (horizontal
synchronization signal)
VSYNCI input (vertical synchronization
signal) fall is modified before output
VSYNCI input (vertical synchronization
signal) fall is modified and the signal is
synchronized with HSYNCI input
(horizontal synchronization signal) before
output
Internal synchronization signal is output
Q
CBLANK signal
(positive)