DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 339

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.7
If bits CKS2 to CKS0 in either TCRY or TCRX are set to B′100, the 2-system 8-bit timers are
cascaded. With this configuration, 16-bit count mode in which the TMRY and TMRX are used as
a single 16-bit timer or compare-match count mode in which the compare-match of the 8-bit timer
(TMRY) is counted by the TMRX can be selected.
11.7.1
When bits CKS2 to CKS0 in TCRY are set to B'100, the timer functions as a single 16-bit timer
with TMRY occupying the upper eight bits and TMRX occupying the lower 8 bits.
Setting of Compare-Match Flags:
• The CMF flag in TCSRY is set to 1 when an upper 8-bit compare-match occurs.
• The CMF flag in TCSRX is set to 1 when a lower 8-bit compare-match occurs.
Counter Clear Specification:
• If the CCLR1 and CCLR0 bits in TCRY have been set for counter clear at compare-match,
• The settings of the CCLR1 and CCLR0 bits in TCRX are valid, and the lower 8 bits of
Pin Output:
• Control of output from the TMOY pin by bits OS3 to OS0 in TCSRY is in accordance with the
• Control of output from the TMOX pin by bits OS3 to OS0 in TCSRX is in accordance with the
11.7.2
When bits CKS2 to CKS0 in TCRX are B'100, TCNTX counts the occurrence of compare-match
A for the TMRY. TMRY and TMRX are controlled independently. Conditions such as setting of
the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in
accordance with the settings for the TMRY and TMRX.
only the upper eight bits of TCNTY are cleared. The upper eight bits of TCNTY are also
cleared when counter clear by the TMRIY pin has been set.
TCNTX can be cleared.
upper 8-bit compare-match conditions.
lower 8-bit compare-match conditions.
TMRY and TMRX Cascaded Connection
16-Bit Count Mode
Compare-Match Count Mode
Rev.2.00 May. 28, 2009 Page 299 of 732
REJ09B0059-0200