DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 455

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.4.8
With the VSYNCO output, the meaning of the signal source to be selected and use or non-use of
modification varies according to the IVI signal source and the waveform required by an external
circuitry. The VSYNCO output modes are shown in table 13.12.
Table 13.12 VSYNCO Output Modes
Mode
No signal
S-on-G mode
or composite
mode
VSYNCO Output
IVI Signal
VFBACKI
input
PDC signal
IVO Signal
IVI signal (without fall
modification or IHI
synchronization)
IVI signal (without fall
modification, with IHI
synchronization)
IVI signal (with fall
modification, without IHI
synchronization)
IVI signal (with fall
modification and IHI
synchronization)
IVG signal
IVI signal (without fall
modification or IHI
synchronization)
IVI signal (without fall
modification, with IHI
synchronization)
IVI signal (with fall
modification, without IHI
synchronization)
IVI signal (with fall
modification and IHI
synchronization)
IVG signal
Meaning of IVO Signal
VFBACKI input is output directly
Meaningless if VFBACKI input is
synchronized with HFBACKI input
VFBACKI input fall is modified before
output
VFBACKI input fall is modified and the
signal is synchronized with HFBACKI
input before output
Internal synchronization signal is output
Vertical synchronization signal part of
CSYNCI/HSYNCI input (composite
synchronization signal) is separated
before output
Vertical synchronization signal part of
CSYNCI/HSYNCI input (composite
synchronization signal) is separated, and
the signal is synchronized with
CSYNCI/HSYNCI input before output
Vertical synchronization signal part of
CSYNCI/HSYNCI input (composite
synchronization signal) is separated, and
fall is modified before output
Vertical synchronization signal part of
CSYNCI/HSYNCI input (composite
synchronization signal) is separated, fall
is modified, and the signal is
synchronized with CSYNCI/HSYNCI input
before output
Internal synchronization signal is output
Rev.2.00 May. 28, 2009 Page 415 of 732
REJ09B0059-0200