DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 338

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.6
If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 2-system 8-bit timers are
cascaded. With this configuration, 16-bit count mode in which the TMR0 and TMR1 are used as a
single 16-bit timer or compare-match count mode in which the compare-match of the 8-bit timer
(TMR0) is counted by the TMR1 can be selected.
11.6.1
When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer
with TMR0 occupying the upper eight bits and TMR1 occupying the lower 8 bits.
Setting of Compare-Match Flags:
• The CMF flag in TCSR0 is set to 1 when a 16-bit compare-match occurs.
• The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare-match occurs.
Counter Clear Specification:
• If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare-match, the
• The settings of the CCLR1 and CCLR0 bits in TCR1 are invalid. The lower 8 bits cannot be
Pin Output:
• Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with the
• Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with the
11.6.2
When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts the occurrence of compare-match A
for the TMR0. The TMR0 and TMR1 are controlled independently. Conditions such as setting of
the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in
accordance with the settings for the TMR0 and TMR1.
Rev.2.00 May. 28, 2009 Page 298 of 732
REJ09B0059-0200
16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare-match occurs.
The 16-bit counter (TCNT0 and TCNT1 together) is also cleared when counter clear by the
TMI0 pin has been set.
cleared independently.
16-bit compare-match conditions.
lower 8-bit compare-match conditions.
TMR0 and TMR1 Cascaded Connection
16-Bit Count Mode
Compare-Match Count Mode