DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 26

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Section 8 8-Bit PWM Timer (PWM)
Figure 8.1
Figure 8.2
Section 9 14-Bit PWM Timer (PWMX)
Figure 9.1
Figure 9.2
Figure 9.3
Rev.2.00 May. 28, 2009 Page xxiv of xxxviii
REJ09B0059-0200
Access Sizes and Data Alignment Control (8-Bit Access Space)........................ 104
Access Sizes and Data Alignment Control (16-Bit Access Space)...................... 105
Bus Timing for 8-Bit, 2-State Access Space........................................................ 107
Bus Timing for 8-Bit, 3-State Access Space........................................................ 108
Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access) ..................... 109
Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access) ...................... 110
Bus Timing for 16-Bit, 2-State Access Space (Word Access)............................. 111
Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access) ..................... 112
Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) ...................... 113
Bus Timing for 16-Bit, 3-State Access Space (Word Access)............................. 114
Bus Timing for 8-Bit, 2-State Data Access Space (With Address Wait) ............. 115
Bus Timing for 8-Bit, 2-State Data Access Space (Without Address Wait)........ 116
Bus Timing for 8-Bit, 3-State Data Access Space (With Address Wait) ............. 117
Bus Timing for 16-Bit, 2-State Data Access Space (1)
(Even Byte Access, with Address Wait) .............................................................. 118
Bus Timing for 16-Bit, 2-State Data Access Space (2)
(Even Byte Access, without Address Wait) ......................................................... 119
Bus Timing for 16-Bit, 2-State Access Space (3)
(Odd Byte Access, with Address Wait) ............................................................... 120
Bus Timing for 16-Bit, 2-State Data Access Space (4)
(Odd Byte Access, without Address Wait) .......................................................... 121
Bus Timing for 16-Bit, 2-State Data Access Space (5)
(Word Access, with Address Wait)...................................................................... 122
Bus Timing for 16-Bit, 2-State Data Access Space (6)
(Word Access, without Address Wait) ................................................................ 123
Bus Timing for 16-Bit, 3-State Data Access Space (1)
(Even Byte Access, with Address Wait) .............................................................. 124
Bus Timing for 16-Bit, 3-State Data Access Space (2)
(Odd Byte Access, with Address Wait) ............................................................... 125
Bus Timing for 16-Bit, 3-State Data Access Space (3)
(Word Access, with Address Wait)...................................................................... 126
Example of Wait State Insertion Timing (Normal Extended Pin Wait Mode) .... 128
Example of Wait State Insertion Timing (Multiplex Extended Mode)................ 129
Examples of Idle Cycle Operation ....................................................................... 130
Block Diagram of PWM Timer ........................................................................... 224
Example of Additional Pulse Timing (When Upper 4 Bits in PWDR = 1000).... 231
Block Diagram of PWMX (D/A)......................................................................... 233
PWMX (D/A) Operation...................................................................................... 241
Output Waveform (OS = 0, DADR Corresponds to T
L
) ...................................... 243