DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 280

IC H8S/2437 MCU FLASH 128QFP

DF2437FV

Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of DF2437FV

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2437FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.4
DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the
on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these
registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written to and
read from as follows.
(1) Write
When the upper byte is written to, the upper-byte write data is stored in TEMP. Next, when the
lower byte is written to, the lower-byte write data and TEMP value are combined, and the
combined 16-bit value is written to the register.
(2) Read
When the upper byte is read from, the upper-byte value is transferred to the CPU and the lower-
byte value is transferred to TEMP. Next, when the lower byte is read from, the lower-byte value in
TEMP is transferred to the CPU.
These registers should always be accessed in 16-bit units at a time with a MOV instruction, and
the upper byte should always be accessed before the lower byte. Correct data will not be
transferred if only the upper byte or only the lower byte is accessed. Also note that a bit
manipulation instruction cannot be used to access these registers.
Example 1: Write to DACNT
Example 2: Read DADRA
Table 9.3
[Legend]
Rev.2.00 May. 28, 2009 Page 240 of 732
REJ09B0059-0200
Register
DADRA, DADRB
DACNT
MOV.W R0, @DACNT
MOV.W @DADRA, R0
×: The result is not guaranteed in that access.
Bus Master Interface
: Indicates the allowed access. Word access includes continuous access to upper bytes
and lower bytes in that order.
Access Method for Reading/Writing 16-Bit Registers
Word
; Write R0 contents to DACNT
; Copy contents of DADRA to R0
Read
Byte
×
Word
Write
Byte
×
×

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