DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 545

IC H8S/2437 MCU FLASH 128QFP

DF2437FV

Manufacturer Part Number
DF2437FV
Description
IC H8S/2437 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheets

Specifications of DF2437FV

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2437FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
17.3.4
ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be
transmitted, and confirms acknowledge bits to be received.
Bit Bit Name
2
1
0
Bit Bit Name
7
6
BC2
BC1
BC0
TIE
TEIE
I
2
C Bus Interrupt Enable Register (ICIER)
Initial Value R/W
0
0
0
Initial Value R/W
0
0
R/W
R/W
R/W
R/W
R/W
Description
Bit Counter 2 to 0
Specify the number of bits to be transferred next. The data
is transferred with one acknowledge bit added. BC2 to BC0
settings should be made during an interval between
transfer frames. If bits BC2 to BC0 are set to a value other
than 000, the setting should be made while the SCL signal
is low. The value automatically returns to B′000 at the end
of a data transfer, including the acknowledge bit.
000: 9 bits
001: 2 bits
010: 3 bits
011: 4 bits
100: 5 bits
101: 6 bits
110: 7 bits
111: 8 bits
Description
Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables or
disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is disabled.
1: Transmit data empty interrupt request (TXI) is enabled.
Enables or disables the transmit end interrupt (TEI) at the
rising of the ninth clock while the TDRE bit in ICSR is 1.
The TEI can be canceled by clearing the TEND bit or the
TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
Transmit End Interrupt Enable
Rev.2.00 May. 28, 2009 Page 505 of 732
Section 17 I
2
C Bus Interface 3 (IIC3)
REJ09B0059-0200

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