DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 552

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 I
17.3.10 I
ICSRA confirms slave address recognition flags.
17.3.11 I
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the I
ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data in ICDRS, continuous transfer is possible.
17.3.12 I
ICDRR is an 8-bit register that stores the receive data. When one byte of data is received, ICDRR
transfers the received data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore this register cannot be written to by the CPU.
Rev.2.00 May. 28, 2009 Page 512 of 732
REJ09B0059-0200
Bit
7
6
5 to 0 ⎯
Bit Name Initial Value R/W Description
AASA
AASB
2
2
2
C Bus Status Register A (ICSRA)
C Bus Transmit Data Register (ICDRT)
C Bus Receive Data Register (ICDRR)
2
C Bus Interface 3 (IIC3)
2
C bus shift register (ICDRS), it transfers the transmit data which is written in
0
0
All 0
R/W Slave Address Recognition Flag A
R/W Slave Address Recognition Flag B
⎯
In slave receive mode, this flag is set to 1 if the upper 7 bits
in the first frame following a start condition match bits
SVA6 to SVA0 in SARA.
[Setting condition]
•
[Clearing condition]
•
In slave receive mode, this flag is set to 1 if the upper 7 bits
in the first frame following a start condition match bits
SVA6 to SVA0 in SARB.
[Setting condition]
•
[Clearing condition]
•
Reserved
These bits are always read as 0.
When the slave address is detected in slave receive
mode
When 0 is written to AASA after reading AASA = 1
When the slave address is detected in slave receive
mode
When 0 is written to AASB after reading AASB = 1