DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 596

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Flash Memory (0.18-μm F-ZTAT Version)
(2) Download of On-Chip Program
The on-chip program is automatically downloaded by setting the flash key code register (FKEY)
and the SCO bit in the flash code control/status register (FCCS), which are programming/erasing
interface registers.
The flash memory MAT is replaced to the embedded program storage area during downloading.
Since the flash memory MAT cannot be read when programming/erasing, the procedure program,
which is working from download to completion of programming/erasing, must be executed in the
space other than the flash memory (for example, on-chip RAM).
Since the result of download is returned to the programming/erasing interface parameter, whether
the normal download is executed or not can be confirmed.
(3) Initialization of Programming/Erasing
The operating frequency is set before execution of programming/erasing. This setting is made by
using the programming/erasing interface parameter.
(4) Programming/Erasing Execution
For programming/erasing execution, the FLSHE bit in SYSCR and the FWE pin must be set to 1
to make a transition to user program mode.
The program data/programming destination address is specified in 128-byte units when
programming. The block to be erased is specified in erase-block units when erasing.
These specifications are set by using the programming/erasing interface parameter and the on-chip
program is initiated. The on-chip program is executed by using the JSR or BSR instruction and
performing the subroutine call of the specified address in the on-chip RAM. The execution result
is returned to the programming/erasing interface parameter.
The area to be programmed must be erased in advance when programming flash memory. All
interrupts must be disabled during programming and erasing. Interrupts must be masked within the
user system.
(5) When Programming/Erasing is Executed Consecutively
When the processing is not ended by the 128-byte programming or one-block erasure, the program
address/data and erase-block number must be updated to perform programming/erasing
consecutively.
Since the downloaded on-chip program is left in the on-chip RAM after the processing, download
and initialization are not required when the same processing is executed consecutively.
Rev.2.00 May. 28, 2009 Page 556 of 732
REJ09B0059-0200