DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 521

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.6.3
Figure 16.16 shows an example of SCI operation for transmission in clocked synchronous mode.
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
3. 8-bit data is output from the TxD pin synchronized with the output clock when output clock
4. The SCI checks the TDRE flag at the timing for sending the last bit.
5. If the TDRE flag is cleared to 0, the next transmit data is transferred from TDR to TSR, and
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the SCI maintains the output
Figure 16.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the
RE bit to 0 does not clear the receive error flags.
TDR, and transfers the data from TDR to TSR.
transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated.
If the TXI interrupt routine writes the next transmit data to TDR before transmission of the
current transmit data has finished, continuous transmission can be enabled.
mode has been specified and synchronized with the input clock when use of an external clock
has been specified.
serial transmission of the next frame is started.
state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is
generated. The SCK pin is fixed high.
Serial Data Transmission (Clocked Synchronous Mode)
Rev.2.00 May. 28, 2009 Page 481 of 732
REJ09B0059-0200