DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 144

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5
The normal extended bus interface enables direct connection between the ROM and SRAM. For
details on the basic area and areas 1 to 3 bus specification selection, refer to tables 6.2 and 6.3.
For multiplex extended bus interface, only products compatible with this bus system can be
directly connected. For details on areas 1 to 3 bus specification selection, refer to tables 6.4 to 6.6
6.5.1
Data sizes for the CPU are byte, word, and longword. The BSC has a data alignment function, and
controls whether the upper data bus (D15 to D8/AD15 to AD8) or lower data bus (D7 to D0/AD7
to AD0) is used when the external address space is accessed, according to the bus specifications
for the area being accessed (8-bit access space or 16-bit access space) and the data size. The
multiplex extended address cycle is fixed to the bus specifications of the area being accessed (8-bit
access space or 16-bit access space).
8-Bit Access Space:
Figure 6.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space,
the upper data bus (D15 to D8/AD15 to AD8) is always used for accesses. The amount of data that
can be accessed at one time is one byte. A word access is performed as two byte accesses, and a
longword access, as four byte accesses.
Rev.2.00 May. 28, 2009 Page 104 of 732
REJ09B0059-0200
Bus Interface
Data Size and Data Alignment
Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space)
Byte size
Word size
Longword
size
1st bus cycle
2nd bus cycle
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
D15/
AD15
Upper data bus
D8/
AD8 AD7
D7/
Lower data bus
D0/
AD0