HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 13

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HD6417706

Manufacturer Part Number
HD6417706
Description
Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Item
10.3 Clock Operating Modes 294
Section 11 Watchdog Timer
(WDT)
Figure 11.1 Block Diagram of
the WDT
11.2.1 Watchdog Timer
Counter (WTCNT)
11.2.2 Watchdog Timer
Control/Status Register
(WTCSR)
12.5.2 Status Flag Clear
Timing
Figure 12.9 Status Flag
Clear Timing
13.3.9 Second Alarm
Register (RSECAR)
Page
297
303
304
304
323
333
Revision (See Manual for Details)
Description amended
Table 10.2 shows the relationship between the mode control pin
(MD2 to MD0) combinations and the clock operating modes. Table
10.3 shows the usable frequency ranges in the clock operating
modes and frequency ranges of the input clock (crystal oscillation).
Operation cannot be guaranteed if settings other than those listed in
table 10.3 are used.
Caution 4 amended
4. The frequency of the peripheral clock (P ):
Figure 11.1 amended
Description amended
the RESETP pin.
Description amended
the RESETP pin.
Figure 12.9 amended
Bit 7 R/W amended
(Before) R
cancellation
Peripheral address bus
Interrupt
Standby
The WTCNT is initialized to H'00 only by a power-on reset through
The WTCSR is initialized to H'00 only by a power-on reset through
The frequency of the peripheral clock (P ) is the product of the
frequency of the CKIO pin, the frequency multiplication ratio of
PLL circuit 1, and the division ratio of divider 2.
Internal
request
request
reset
UNF, ICPF
(After) R/W
Standby
Interrupt
P
control
control
control
Reset
WTCSR
Clock selection
Overflow
Bus interface
WDT
Rev. 4.00, 03/04, page xiii of xlvi
T1
TCR write cycle
WTCNT
TCR address
T2
Clock selector
Divider
Clock
T3
Standby
mode
Peripheral
clock

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