HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 134

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

4.2.3
The interrupt event register 2 (INTEVT2) contains a 12-bit exception code. The exception code set
in INTEVT2 is that for an interrupt request. The exception code is set automatically by hardware
when an exception occurs.
4.2.4
The TRAPA exception register (TRA) contains 8-bit immediate data (imm) for the TRAPA
instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA
can also be modified by software.
Rev. 4.00, 03/04, page 88 of 660
Bit
31 to 12
11 to 0
Bit
31 to 12
11 to 0
Bit
31 to 10
9 to 2
1, 0
Interrupt Event Register 2 (INTEVT2)
TRAPA Exception Register (TRA)
Bit Name
Bit Name
Bit Name
imm
Initial Value R/W
All 0
Initial Value R/W
All 0
Initial Value R/W
All 0
All 0
R
R/W
R
R/W
R
R/W
R
These bits are always read as 0. The write value
should always be 0.
12-bit interrupt exception code or a code indicating
the interrupt priority
These bits are always read as 0. The write value
should always be 0.
12-bit exception code
These bits are always read as 0. The write value
should always be 0.
8-bit immediate data
These bits are always read as 0. The write value
should always be 0.
Description
Reserved
Description
Reserved
Description
Reserved
Reserved