HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 181

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The UBC provides functions that simplify program debugging. Using this function, a self-monitor
debugger can be easily prepared, and a program can be debugged using this LSI alone, without
using an in-circuit emulator. Instruction fetches, data read/write, data size, data contents, address
values, and the timing to stop execution at instruction fetch can be set to the UBC. The UBC
block diagram is shown in figure 7.1.
7.1
The UBC has the following features:
The following break comparison conditions can be set.
Number of break channels: (channels A and B)
Address: comparison bits are masked in units of 32 bits.
One of the two address buses (the virtual address bus (LAB) and the internal address bus
(IAB)) can be selected
Data: only on channel B, 32-bit maskable
One of two data buses (the virtual data bus (LDB) or the internal data bus (IDB)) can be
selected.
Bus master: CPU cycle or DMAC cycle
Bus cycle: instruction fetch or data access
Read/write
Operand size: byte, word, or longword
A user-designed user-break condition exception processing routine can be run.
In an instruction fetch cycle, it can be selected that a break is set before or after an instruction
is executed.
The number of repeat times can be specified as a break condition (It is only for channel B).
Maximum repeat times for the break condition: 2
Eight pairs of branch source/destination buffers.
Feature
Section 7 User Break Controller
12
– 1 times.
Rev. 4.00, 03/04, page 135 of 660