HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 445

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The receive margin in the asynchronous mode can therefore be expressed as in equation 1.
Equation 1:
Where:
M
N
D
L
F
From equation 1, if F
Equation 2:
This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30%.
Cautions for Clock Synchronous External Clock Mode:
Caution for Clock Synchronous Internal Clock Mode: In the receiving, RDRF become 1 when
RE is set to 0, 1.5 clocks after the rising edge of the SCK0 output of the D7 bit in RxD0, but it
cannot be copied to SCRDR.
Set TE = RE = 1 only when the external clock SCK0 is 1.
Do not set TE = RE = 1 until at least four clocks after the external clock SCK0 has changed
from 0 to 1.
When receiving, RDRF is 1 when RE is set to zero 2.5–3.5 clocks after the rising edge of the
SCK0 input of the D7 bit in RxD0, but it cannot be copied to SCRDR.
Absolute deviation of clock frequency
Frame length (L
Ratio of clock frequency to bit rate (N
Clock duty cycle (D
Receive margin ( )
M
M = 0.5 –
(0.5 – 1/(2
46.875
2N
1
9 to 12)
0 and D
– (L – 0.5)F –
16))
0 to 1.0)
100
0.5, the receive margin is 46.875%, as in equation 2.
D – 0.5
N
16)
(1 + F)
100%
Rev. 4.00, 03/04, page 399 of 660