HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 476

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 4.00, 03/04, page 430 of 660
Bit
5
4
3, 2
1
0
Bit Name
TE
RE
—
CKE1
CKE0
Initial Value
All 0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Transmit Enable
Enables or disables the SCIF serial transmitter.
0: Transmitter disabled.
1: Transmitter enabled.
Receive Enable
Enables or disables the SCIF serial receiver.
0: Receiver disabled.
1: Receiver enabled.
These bits are always read as 0. The write value
should always be 0.
Clock Enable
These bits select the SCIF clock source and enable
or disable clock output from the SCK2 pin.
Depending on the combination of CKE1 and CKE0,
the SCK2 pin can be used for serial clock output or
serial clock input.
The CKE0 setting is valid only when the SCI is
operating with the internal clock (CKE1
CKE0 setting is ignored when an external clock
source is selected (CKE1
SCIF operating mode in the SCSMR2, before
setting CKE1 and CKE0. For further details on
selection of the SCIF clock source, see table 16.7
in section 16.4, Operation.
00: Internal clock, SCK pin used for input pin (input
01: Internal clock, SCK2 pin used for clock output*
10: External clock, SCK2 pin used for clock input*
11: External clock, SCK2 pin used for clock input*
Notes: 1. The output clock frequency is 16 times
Reserved
Note: Serial transmission starts after writing of
transmit data into the SCFTDR2. Select the
transmit format in the SCSMR2 and SCFCR2
and reset the TFIFO before setting TE to 1.
Note: Clearing RE to 0 does not affect the
receive flags (DR, ER, BRK, FER and PER).
These flags retain their previous values.
Note: Serial reception starts when a start bit is
detected. Select the receive format in the
SCSMR2 before setting RE to 1.
signal is ignored)
2. The input clock frequency is 16 times the
the bit rate.
bit rate.
1). Always select the
0). The
2
2
1