HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 289

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

This chip includes a four-channel direct memory access controller (DMAC). The DMAC can be
used in place of the CPU to perform high-speed transfers between external devices that have
DACK (transfer request acknowledge signal), external memory, memory-mapped external devices,
and on-chip peripheral modules (SCIF, A/D converter, and D/A converter). Using the DMAC
reduces the burden on the CPU and increases overall operating efficiency.
Figure 9.1 shows a block diagram of the DMAC.
9.1
The DMAC has the following features.
Four channels
Address space: Architecturally 4-Gbytes
8-bit, 16-bit, 32-bit, or 16-byte transfer (In 16-byte transfer, four 32-bit reads are executed,
followed by four 32-bit writes.)
Maximum transfer counter: 16 Mbytes (16777216 transfers)
Supports dual address mode
Supports single address mode
Channel functions: Transfer mode that can be specified is different in each channel.
Reload function: The value that was specified in the source address register can be
automatically reloaded every 4 DMA transfers. This function is only valid in channel 2.
Section 9 Direct Memory Access Controller (DMAC)
Direct address transfer mode: The values specified in the DMAC registers indicates the
transfer source and transfer destination. Two bus cycles are required for one data transfer.
Indirect address transfer mode: Data is transferred with the address stored prior to the
address specified in the transfer source address in the DMAC. Other operations are the
same as those of direct address transfer mode. This function is only valid in channel 3.
Four bus cycles are required for one data transfer.
Either the transfer source or transfer destination peripheral device is accessed (selected) by
means of the DACK signal, and the other device is accessed by address. One bus cycle is
required for one data transfer.
Channel 0: External request can be accepted.
Channel 1: External request can be accepted.
Channel 2: This channel has a source address reload function, which reloads a source
Channel 3: In this channel, direct address transfer mode or indirect address transfer mode
Feature
can be specified.
address for each 4 transfers.
Rev. 4.00, 03/04, page 243 of 660