HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 98

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Although the functions of the MMU could also be implemented by software alone, the need for
translation to be performed by software each time a process accesses physical memory would
result in poor efficiency. For this reason, a buffer for address translation (translation look-aside
buffer: TLB) is provided in hardware to hold frequently used address translation information. The
TLB can be described as a cache for storing address translation information. Unlike cache
memory, however, if address translation fails, that is, if an exception is generated, switching of
address translation information is normally performed by software. This makes it possible for
memory management to be performed flexibly by software.
The MMU has two methods of mapping from virtual memory to physical memory: a paging
method using fixed-length address translation, and a segment method using variable-length
address translation. With the paging method, the unit of translation is a fixed-size address space
(usually of 1 to 64 kbytes) called a page.
In the following text, this LSI's address space in virtual memory is referred to as virtual address
space, and address space in physical memory as physical memory space.
Rev. 4.00, 03/04, page 52 of 660
Process 1
Physical
memory
Process 1
Process 1
Process 2
Process 3
Figure 3.1 MMU Functions
Physical
memory
Physical
memory
(3)
(1)
Process 1
Process 1
Process 2
Process 3
Virtual
memory
Virtual
memory
MMU
MMU
Physical
memory
Physical
memory
(4)
(2)