HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 185
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HD6417706
Manufacturer Part Number
HD6417706
Description
Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417706.pdf
(709 pages)
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Note:
7.2.4
BARB is a 32-bit read/write register. BARB specifies the address used as a break condition in
channel B.
Bit
5
4
3
2
1
0
Bit
31 to 0
X Don't care
Break Address Register B (BARB)
Bit Name
IDA1
IDA0
RWA1
RWA0
SZA1
SZA0
Bit Name
BAB31 to
BAB0
Initial Value R/W
All 0
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Break Address
Stores the address of LAB or IAB that specifies the
break conditions of channel B.
Description
Instruction Fetch/Data Access Select A
Selects the instruction fetch cycle or data access
cycle as the bus cycle of the channel A break
condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch
10: The break condition is the data access cycle
11: The break condition is the instruction fetch
Read/Write Select A
Selects the read cycle or write cycle as the bus
cycle of the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write
Operand Size Select A
Selects the operand size of the bus cycle for the
channel A break condition.
00: The break condition does not include
11: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
cycle
cycle or data access cycle
cycle
operand size
Rev. 4.00, 03/04, page 139 of 660
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