HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 564

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

21.1
The H-UDI has the following features.
21.2
Table 21.1 lists the pin configuration of the H-UDI.
Table 21.1 Pin Configuraiton
Rev. 4.00, 03/04, page 518 of 660
Name
TCK
TMS
TRST
TDI
TDO
ASEMD0
ASEBRKAK
Support of the E10A emulator
Standard pin arrangement of JTAG
Real-time branch trace
1-kbyte on-chip RAM for running the high-speed emulation program
Input/Output Pin
Feature
Description
H-UDI serial data input/output clock pin. Data is serially supplied to the H-UDI
from the data input pin (TDI), and output from the data output pin (TDO), in
synchronization with this clock.
Mode select input pin. The state of the TAP control circuit is determined by
changing this signal in synchronization with TCK. The protocol conforms to the
JTAG standard (IEEE Std. 1149.1).
H-UDI reset input pin. Input is accepted asynchronously with respect to TCK, and
when low, the H-UDI is reset. See section 21.4.2, Reset Configuration, for more
information.
H-UDI serial data input pin. Data transfer to the H-UDI is executed by changing
this signal in synchronization with TCK.
H-UDI serial data output pin. Data output from the H-UDI is executed by reading
this signal in synchronization with TCK.
ASE mode select pin. If a low level is input at the ASEMD0 pin while the RESETP
pin is asserted, ASE mode is entered; if a high level is input, normal operation
mode is entered. ASEMD0 pin should be high level when an emulator or H-UDI is
not used. In ASE mode, boundary scan and emulator functions can be used. The
input level at the ASEMD0 pin should be held for at least one cycle after RESETP
negation.
Dedicated emulator pin