HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 290

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 4.00, 03/04, page 244 of 660
Three types of Transfer requests
Selectable bus modes: Cycle-steal mode or burst mode
Selectable channel priority levels
Interrupt request: An interrupt request can be generated to the CPU after transfers end by the
specified counts.
External request: From two DREQ pins (channels 0 and 1 only). DREQ can be detected
either by the falling edge or by the low level.
On-chip module request: Requests from on-chip peripheral modules such as serial
communications interface (SCIF), A/D converter (A/D), and a timer (CMT). This request
can be accepted in all the channels.
Auto request: The transfer request is generated automatically within the DMAC.
Fixed mode: The channel priority is fixed.
Round-robin mode: The priority of the channel in which the execution request was
accepted is made the lowest.
acknowledge)
External I/O
External I/O
peripheral
(memory
mapped)
External
External
On-chip
module
ROM
DACK0, DACK1
DRAK0, DRAK1
RAM
(with
A/D converter
,
DEI_n
SCIF
CMT
Figure 9.1 DMAC Block Diagram
Bus state
controller
Legend
DMAOR:
SAR_n:
DAR_n:
DMATCR_n:
CHCR_n:
DEI_n:
n:
Bus interface
Interation
Register
Request
Start-up
control
control
control
priority
control
DMAC operation register
DMAC source address register
DMAC destination address register
DMAC transfer count register
DMAC channel control register
DMA transfer-end interrupt request to
CPU
0 to 3
DMAC module
DMATCR_n
CHCR_n
DMAOR
DAR_n
SAR_n