HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 424

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0, the SCI
2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new
Figure 14.9 shows an example of SCI transmit operation in the asynchronous mode.
Rev. 4.00, 03/04, page 378 of 660
recognizes that the transmit data register (SCTDR) contains new data, and loads this data from
the SCTDR into the SCTSR.
starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the
SCSCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit
data is transmitted in the following order from the TxD0 pin:
a. Start bit: One 0 bit is output.
b. Transmit data: Seven or eight bits of data are output, LSB first.
c. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor
d. Stop bit: One or two 1 bits (stop bits) are output.
e. Marking: Output of 1 bits continues until the start bit of the next transmit data.
data from the SCTDR into the SCTSR, outputs the stop bit, then begins serial transmission of
the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in the SCSSR, outputs the stop
bit, then continues output of 1 bits (marking). If the transmit-end interrupt enable bit (TEIE) in
the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested.
Example: 8-bit data with parity and one stop bit
TXI interrupt
TDRE
TEND
generated
Serial
bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can
also be selected.
request
data
1
Figure 14.9 SCI Transmit Operation in Asynchronous Mode
Start
bit
0
processing routine
SCTDR with the
and clear TDRE
Writes data to
TXI interrupt
D 0
bit to 0
D 1
1 frame
Data
D 7
TXI interrupt
Parity
generated
request
bit
0/1
Stop
bit
1
Start
0
bit
D 0
D 1
Data
D 7
Parity
bit
0/1
TEI interrupt
generated
request
Stop
bit
1
(marking)
Idling
1