HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 490

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HD6417706

Manufacturer Part Number
HD6417706
Description
Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Rev. 4.00, 03/04, page 444 of 660
Bit
5
4
3
2
1
0
Bit Name
TTRG1
TTRG0
MCE
TFRST
RFRST
LOOP
Initial Value R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Trigger of the Number of Transmit FIFO Data
Set the reference number of the send data empty.
The TDFE in SCSSR2 is set to 1, when the
transmitting data count has fallen the following trigger
number.
00:
01:
10:
11:
Note: Values in brackets mean the number of empty
Modem Control Enable
Enables the modem control signals CTS2 and RTS2.
0: Disables the modem signal*
1: Enables the modem signal
Note: * The CTS2 is fixed to active 0 regardless of the
Cancels the transmit data in the SCFTDR2 and resets
the data to the empty state.
0: Disables reset operation*
1: Enables reset operation
Note: * The reset is executed in a hardware reset or
Receive FIFO Data Register Reset
Cancels the receive data in the SCFRDR2 and resets
the data to the empty state.
0: Disables reset operation*
1: Enables reset operation
Note: * The reset is executed in a hardware reset or
Loop Back Test
Internally connects the transmit output pin (TXD2) and
receive input pin (RXD2) and enables the loop back
test.
0: Disables the loop back test
1: Enables the loop back test
Description
Transmit FIFO Data Register Reset
Trigger number of transmit data.
bytes in SCFTDR when the TDFE is set.
input value, and the RTS2 is also fixed to 0.
the standby mode.
the standby mode.
8 (8)
4 (12)
2 (14)
1 (15)

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