HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 363

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.3.4
TCOR_0 to TCOR_2 are specified the setting value for TCNT_0 to TCNT_2 when TCNT_0 to
TCNT_2 are underflowed. TMU has 3 timer constant registers, one for each channel.
TCOR_0 to TCOR_2 is a 32-bit read/write register. TCOR is initialized to H'FFFFFFFF by a
power-on reset or manual reset; it is not initialized in standby mode, and retains its contents.
Bit
5
4
3
2
1
0
Timer Constant Registers 0 to 2 (TCOR_0 to TCOR_2)
Bit Name
UNIE
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Initial Value R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Underflow Interrupt Control
Controls enabling of interrupt generation when the
status flag (UNF) indicating TCNT_2 underflow has
been set to 1.
0: Interrupt due to UNF (TUNI) is not enabled.
1: Interrupt due to UNF (TUNI) is enabled.
Clock Edge
These bits select the external clock edge when the
external clock is selected, or when the input capture
function is used.
00: Count/capture register set on rising edge
01: Count/capture register set on falling edge
1X: Count/capture register set on both rising and
Note: X: Don't care.
Timer Prescalers
These bits select the TCNT_2 count clock.
000: Internal clock: count on P /4
001: Internal clock: count on P 16
010: Internal clock: count on P /64
011: Internal clock: count on P /256
100: Internal clock: count on clock output of on-chip
101: External clock: count on TCLK pin input
110: Reserved (Setting prohibited)
111: Reserved (Setting prohibited)
falling edge
RTC (RTCCLK)
Rev. 4.00, 03/04, page 317 of 660