HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 255

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 8.18 Example of Correspondence between this LSI and Synchronous DRAM
Figure 8.13 shows the timing chart for a burst read. In the example below, it is assumed that four
2M
length is 1. Following the Tr cycle in which ACTV command output is performed, a READ
command is issued in the Tc1, Tc2, and Tc3 cycles, and a READA command in the Tc4 cycle, and
the read data is accepted on the rising edge of the external command clock (CKIO) from cycle Td1
to cycle Td4. The Tpc cycle is used to wait for completion of auto-precharge based on the
READA command inside the synchronous DRAM; no new access command can be issued to the
same bank during this cycle, but access to synchronous DRAM for another area is possible. In the
this LSI, the number of Tpc cycles is determined by the TPC bit specification in MCR, and
commands cannot be issued for the same synchronous DRAM during this interval.
Address Pin of this LSI
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Burst Read
8-bit synchronous DRAMs are connected and a 32-bit data width is used, and the burst
Address Pins (AMX (3 to 0) = 0100 (32-Bit Bus Width))
RAS Cycle
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
CAS Cycle
A23
A22
A13
L/H
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Synchronous DRAM Address Pin
A13(BA1)
A12(BA0)
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Not used
Not used
Rev. 4.00, 03/04, page 209 of 660
Function
BANK select address
Address
Address/precharge setting
Address