HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 432

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Receiving Multiprocessor Serial Data: Figure 14.15 shows a sample flowchart for receiving
multiprocessor serial data. Reception of multiprocessor serial data should be carried out in the
following procedure after setting the SCI in a reception-enabled state.
Rev. 4.00, 03/04, page 386 of 660
Figure 14.15 Sample Flowchart for Receiving Multiprocessor Serial Data
No
No
No
Read receive data in SCRDR
Read receive data in SCRDR
Set MPIE bit in SCSCR to 1
Clear RE bit in SCSCR to 0
Read RDRF bit in SCSSR
Read RDRF bit in SCSSR
FER = 1 or ORER = 1?
FER = 1 or ORER = 1?
Read ORER and FER
Read ORER and FER
All data received?
Start reception
bits in SCSSR
bits in SSCSR
End reception
RDRF = 1?
stations ID?
RDRF = 1?
Yes
Is ID the
Yes
Yes
Yes
No
No
Yes
Yes
No
Error processing
1.
2.
3.
4.
ID receive cycle: Set the MPIE
bit in SCSCR to 1.
SCI status check and compare
to ID reception: Read the SCSSR,
check that RDRF is set to 1, then
read data from the SCRDR and
compare with the processor's own
ID. If the ID does not match the
receive data, set MPIE to 1 again
and clear RDRF to 0. If the ID
matches the receive data, clear
RDRF to 0.
SCI status check and data receiving:
Read SCSSR, check that RDRF is
set to 1, then read data from the
SCRDR.
Receive error processing and break
detection: If a receive error occurs,
read the ORER and FER bits in
SCSSR to identify the error. After
executing the necessary error
processing, clear both ORER and
FER to 0. Receiving cannot resume
if ORER or FER remain set to 1.
When a framing error occurs, the
RxD0 pin can be read to detect the
break state.