HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 17

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
19.4 Bus Master Interface
Figure 19.2 A/D Data
Register Access Operation
(Reading H'AA40)
19.6.3 Scan Mode (MULTI =
1, SCN = 1)
Figure 19.7 Example of A/D
Converter Operation (Scan
Mode, Channels AN0 to AN2
Selected)
19.6.4 Input Sampling and
A/D Conversion Time
19.9.1 Setting Analog Input
Voltage
21.3.3 Boundary Scan
Register (SDBSR)
Table 21.2 This LSI's Pins
and Boundary Scan Register
Bits
21.4.1 TAP Controller
Page
502
507
508
511
522
525
Revision (See Manual for Details)
Figure 19.2 amended
Lower byte read
Figure 19.7 amended
Set*
ADDRA*
Notes: 1. Downward arrows indicate instruction executed by
Description deleted
In multi mode and scan mode, the values given in table 19.3 apply to
the first conversion. In the second and subsequent conversions the
conversion time is fixed at 512 states when CKS = 0 or 256 states
when CKS = 1.
Description amended
Table 21.2 amended
Bit 171 I/O
(Before) (blank)
Bit 160 I/O
(Before) OUT
Note amended
Note:
SR) and shift-IR states. When TRST = 0, there is a transition to test-
logic-reset asynchronously with TCK.
Analog Input Voltage Range: During A/D conversion, the voltages
input to the analog input pins ANn should be in the range AV
ANn
AV
follows: AVcc = VccQ ± 0.2 V and AVss = Vss.
(H'40)
CPU
1
CC
2. Data is ignored during conversion.
, Avss, Input Voltage: AVcc and AVss should be related as
2
The TDO is at high impedance, except with shift-DR (shift-
AV
software.
Clear*
ADDRB*
CC
(n = 0 to 3).
(After) Control
1
(After) OUT
2
interface
Bus
ADDRC*
A/D data register
Upper byte of
2
Rev. 4.00, 03/04, page xvii of xlvi
(H'AA)
ADDRD*
2
A/D data register
Lower byte of
TEMP
(H'40)
Module internal data bus
(H'40)
SS