HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 60

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 4.00, 03/04, page 14 of 660
31
Notes: 1.
a. User mode register
2.
3.
4.
R0_BANK0*
configuration
R1_BANK0*
R2_BANK0*
R3_BANK0*
R4_BANK0*
R5_BANK0*
R6_BANK0*
R7_BANK0*
R0 functions as an index register in the indexed register-indirect addressing mode and indexed
GBR-indirect addressing mode.
Banked register
Banked register
When the RB bit of the SR register is 1, the register can be accessed for general use. When the
RB bit is 0, it can only be accessed with the LDC/STC instruction.
Banked register
When the RB bit of the SR register is 0, the register can be accessed for general use. When the
RB bit is 1, it can only be accessed with the LDC/STC instruction.
MACH
MACL
GBR
R10
R11
R12
R13
R14
R15
R8
R9
SR
PR
PC
1
2
2
2
2
2
2
2
*
2
Figure 2.1 Register Configuration
0
31
b. Privileged mode
R0_BANK1*
R0_BANK0*
register configuration
(RB = 1)
R1_BANK1*
R2_BANK1*
R3_BANK1*
R4_BANK1*
R5_BANK1*
R6_BANK1*
R7_BANK1*
R1_BANK0*
R2_BANK0*
R3_BANK0*
R4_BANK0*
R5_BANK0*
R6_BANK0*
R7_BANK0*
MACH
MACL
GBR
SSR
VBR
SPC
R10
R11
R12
R13
R14
R15
PR
SR
PC
R8
R9
1
1
3
3
3
3
3
3
3
4
4
4
4
4
4
4
*
*
3
4
0
31
c. Privileged mode
register configuration
(RB = 0)
R0_BANK0*
R0_BANK1*
R1_BANK0*
R2_BANK0*
R3_BANK0*
R4_BANK0*
R5_BANK0*
R6_BANK0*
R7_BANK0*
R1_BANK1*
R2_BANK1*
R3_BANK1*
R4_BANK1*
R5_BANK1*
R6_BANK1*
R7_BANK1*
MACH
MACL
GBR
SSR
VBR
SPC
R10
R11
R12
R13
R14
R15
PR
SR
PC
R8
R9
1
1
4
4
4
4
4
4
4
3
3
3
3
3
3
3
*
*
4
3
0