HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 220

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

8.4.3
Wait state control register 1 (WCR1) is a 16-bit read/write register that specifies the number of
idle (wait) state cycles inserted for each area. For some memories, the drive of the data bus may
not be turned off quickly even when the read signal from the external device is turned off. This
can result in conflicts between data buses when consecutive memory accesses are to different
memories or when a write immediately follows a memory read. This LSI automatically inserts idle
states equal to the number set in WCR1 in those cases.
WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or by
standby mode.
Rev. 4.00, 03/04, page 174 of 660
Bit
5
4
3 to 0
Bit
15
14
Bit Name
A2SZ1
A2SZ0
—
Bit Name
WAITSEL
—
Wait State Control Register 1 (WCR1)
Initial Value
1
1
All 0
Initial Value R/W
0
0
R/W
R
R/W
R/W
R/W
R
Specifies the WAIT signal sampling timing.
0: Set 1 to use the WAIT signal.
1: The WAIT signal is sampled at the falling edge of
Reserved
These bits are always read as 0. The write value
should always be 0.
Description
WAIT Sampling Timing Select
Description
Area 2 Bus Size Specification
Specify the bus sizes of physical space area 2.
00: Reserved (Setting prohibited)
01: Byte (8-bit) size
10: Word (16-bit) size
11: Longword (32-bit) size
00: Reserved (Setting prohibited)
01: Byte (8-bit) size
10: Word (16-bit) size
11: Reserved (Setting prohibited)
Reserved
These bits are always read as 0. The write value
should always be 0.
CKIO.
When port A/B is unused.
When port A/B is used.