HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 208

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

8.3
Space Allocation: In the architecture of this LSI, both logical spaces and physical spaces have 32-
bit address spaces. The logical space is divided into five areas by the value of the upper bits of the
address. The physical space is divided into eight areas.
Logical space can be allocated at physical spaces using a memory management unit (MMU). For
details, refer to section 3, Memory Management Unit (MMU), which describes area allocation for
physical spaces.
As listed in table 8.2, this LSI can be connected directly to six areas of memory/PCMCIA
interface, and it outputs chip select signals (CS0, CS2 to CS6, CE2A, CE2B) for each of them.
CS0 is asserted during area 0 access; CS6 is asserted during area 6 access. When PCMCIA
interface is selected in area 5 or 6, in addition to CS5/CS6, CE2A/CE2B are asserted for the
corresponding bytes accessed.
Rev. 4.00, 03/04, page 162 of 660
Pin Name
Data enable 3
Read
Wait
Clock enable
IOIS16
Bus release request BREQ
Bus release
acknowledgment
Area Overview
CKE
Signal
WE3/DQMUU/
ICIOWR
RD
WAIT
IOIS16
BACK
I/O Description
O
O
I
O
I
I
O
When memory other than synchronous DRAM is used,
selects D31 to D24 write strobe signal. When
synchronous DRAM is used, selects D31 to D24. When
PCMCIA is used, strobe signal indicating I/O write.
Strobe signal indicating read cycle
Wait state request signal
Clock enable control signal of synchronous DRAM
Signal indicating PCMCIA 16-bit I/O. Valid only in little-
endian mode.
Bus release request signal
Bus release acknowledge signal