HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 21

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 1 Overview...........................................................................................
1.1
1.2
1.3
1.4
Section 2 CPU................................................................................................... 13
2.1
2.2
2.3
2.4
2.5
Section 3 Memory Management Unit (MMU) ................................................. 51
3.1
3.2
3.3
Feature...............................................................................................................................
Block Diagram ..................................................................................................................
Pin Assignment .................................................................................................................
Pin Function ......................................................................................................................
Register Description.......................................................................................................... 13
2.1.1
2.1.2
2.1.3
2.1.4
Data Formats ..................................................................................................................... 20
2.2.1
2.2.2
Instruction Features........................................................................................................... 21
2.3.1
2.3.2
2.3.3
Instruction Set ................................................................................................................... 30
2.4.1
2.4.2
Processor States and Processor Modes.............................................................................. 49
2.5.1
2.5.2
Role of MMU.................................................................................................................... 51
3.1.1
Register Description.......................................................................................................... 56
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
TLB Functions .................................................................................................................. 59
3.3.1
3.3.2
3.3.3
Privileged Mode and Banks ................................................................................. 13
General Registers ................................................................................................. 15
System Registers.................................................................................................. 16
Control Registers ................................................................................................. 17
Data Format in Registers...................................................................................... 20
Data Format in Memory....................................................................................... 20
Execution Environment........................................................................................ 21
Addressing Modes ............................................................................................... 23
Instruction Formats .............................................................................................. 27
Instruction Set Classified by Function ................................................................. 30
Instruction Code Map .......................................................................................... 46
Processor States ................................................................................................... 49
Processor Modes .................................................................................................. 50
This LSI's MMU .................................................................................................. 53
Page Table Entry Register High (PTEH) ............................................................. 56
Page Table Entry Register Low (PTEL) .............................................................. 57
The Translation Table Base Register (TTB) ........................................................ 57
The TLB Exception Address Register (TEA) ...................................................... 57
MMU Control Register (MMUCR) ..................................................................... 58
Configuration of the TLB .................................................................................... 59
TLB Indexing....................................................................................................... 61
TLB Address Comparison ................................................................................... 62
Contents
Rev. 4.00, 03/04, page xxi of xlvi
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