HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 22

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

3.4
3.5
3.6
3.7
Section 4 Exception Processing......................................................................... 81
4.1
4.2
4.3
4.4
4.5
Rev. 4.00, 03/04, page xxii of xlvi
MMU Functions................................................................................................................ 65
MMU Exceptions.............................................................................................................. 69
Usage Note........................................................................................................................ 78
Register Description.......................................................................................................... 87
Operation .......................................................................................................................... 89
Individual Exception Operations....................................................................................... 90
Usage Note........................................................................................................................ 96
3.3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
Configuration of the Memory-Mapped TLB .................................................................... 76
3.6.1
3.6.2
3.6.3
3.7.1
3.7.2
Exception Processing Function ......................................................................................... 81
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.2.1
4.2.2
4.2.3
4.2.4
4.3.1
4.3.2
4.3.3
4.4.1
4.4.2
4.4.3
Page Management Information............................................................................ 64
MMU Hardware Management ............................................................................. 65
MMU Software Management .............................................................................. 65
MMU Instruction (LDTLB)................................................................................. 66
Avoiding Synonym Problems .............................................................................. 67
TLB Miss Exception ............................................................................................ 69
TLB Protection Violation Exception ................................................................... 70
TLB Invalid Exception ........................................................................................ 71
Initial Page Write Exception ................................................................................ 72
Processing Flow in Event of MMU Exception
(Same Processing Flow for CPU Address Error)................................................. 74
Address Array ...................................................................................................... 76
Data Array............................................................................................................ 76
Usage Examples................................................................................................... 78
Use of Instructions Manipulating MD and BL Bits in SR ................................... 78
Use of TLB .......................................................................................................... 79
Exception Processing Flow.................................................................................. 81
Exception Processing Vector Addresses.............................................................. 82
Acceptance of Exceptions.................................................................................... 83
Exception Codes .................................................................................................. 85
Exception Request and BL Bit............................................................................. 86
Returning from Exception Processing ................................................................. 86
Exception Event Register (EXPEVT).................................................................. 87
Interrupt Event Register (INTEVT)..................................................................... 87
Interrupt Event Register 2 (INTEVT2)................................................................ 88
TRAPA Exception Register (TRA) ..................................................................... 88
Reset .................................................................................................................... 89
Interrupts.............................................................................................................. 89
General Exceptions .............................................................................................. 90
Resets................................................................................................................... 90
General Exceptions .............................................................................................. 91
Interrupts.............................................................................................................. 94