HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 472

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

16.3.1
The receive shift register 2 (SCRSR2) is an eight-bit register taht receives serial data. The CPU
cannot read from or write to the SCRSR2 directly. Data input at the RxD pin is loaded into the
SCRSR2 in the order received, LSB (bit 0) first, converting the data to parallel form. When one
byte has been received, it is automatically transferred to the SCFRDR2, which is a receive FIFO
register.
16.3.2
The 16-byte receive FIFO data register2(SCFRDR2) stores serial receive data. The SCIF
completes the reception of one byte of serial data by moving the received data from the SCRSR2
into the SCFRDR2 for storage. Continuous receive is possible until 16 bytes are stored.
The CPU can read but not write the SCFRDR2. When data is read without received data in the
SCFRFR2, the value is undefined. When the received data in this register becomes full, the
subsequent serial data is lost.
16.3.3
The transmit shift register 2 (SCTSR2) is an eight-bit register that transmits serial data. The CPU
cannot read from or write to the SCTSR2 directly. The SCI loads transmit data from the
SCFTDR2 into the SCTSR2, then transmits the data serially from the TxD pin, LSB (bit 0) first.
After transmitting one data byte, the SCI automatically loads the next transmit data from the
SCFTDR2 into the SCTSR2 and starts transmitting again.
16.3.4
The transmit FIFO data register 2 (SCFTDR2) is a 16-byte FIFO register that stores data for serial
transmission. When the SCIF detects that the SCTSR is empty, it moves transmit data written in
the SCFTDR2 into the SCTSR2 and starts serial transmission. Continuous serial transmission is
performed until the transmit data in the SCFTDR2 becomes empty. The CPU can always write to
the SCFTDR2.
When the transmit data in the SCFTDR2 is full (16 bytes), next data cannot be written. If
attempted to write, the data is ignored.
16.3.5
The serial mode register2 (SCSMR2) is an eight-bit register that specifies the SCIF serial
communication format and selects the clock source for the baud rate generator.
The CPU can always read and write the SCSMR2.
Rev. 4.00, 03/04, page 426 of 660
Receive Shift Register 2 (SCRSR2)
Receive FIFO Data Register 2 (SCFRDR2)
Transmit Shift Register 2 (SCTSR2)
Transmit FIFO Data Register 2 (SCFTDR2)
Serial Mode Register 2 (SCSMR2)