HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 332

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HD6417706

Manufacturer Part Number
HD6417706
Description
Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the
CMCOR register and the CMCNT counter match. The compare match signal is generated upon the
final state of the match (timing at which the CMCNT counter matching count value is updated).
Consequently, after the CMCOR register and the CMCNT counter match, a compare match signal
will not be generated until a CMCNT counter input clock occurs. Figure 9.29 shows the CMF bit
set timing.
The CMF bit of the CMCSR register is cleared by writing 0 to it after reading 1. Figure 9.30 shows
the timing when the CMF bit is cleared by the CPU.
Rev. 4.00, 03/04, page 286 of 660
Compare Match Flag Set Timing
Compare Match Flag Clear Timing
match signal
input clock
Compare
CMCOR
CMCNT
CMCNT
Figure 9.30 Timing of CMF Clear by the CPU
CMF
CMF
CMI
CK
CK
Figure 9.29 CMF Set Timing
N
N
CMCSR0 write cycle
T
1
T
2
0

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