HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 267

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HD6417706

Manufacturer Part Number
HD6417706
Description
Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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The bus state controller is provided with a function for controlling synchronous DRAM refreshing.
Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1
in MCR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the
power consumption for data retention is low, can be activated by setting both the RMODE bit and
the RFSH bit to 1.
Refreshing
Address
upper bits
A12 or A11
Address
lower bits
CKIO
RD/
D31 to D0
Notes: 1.
or
2.
*
Figure 8.23 Burst Write Timing (Different Row Addresses)
2
*
Command bit
Column address
1
Tp
Tr
Tc1
Tc2
Rev. 4.00, 03/04, page 221 of 660
Tc3
Td4

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