HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 440

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

In receiving, the SCI operates as follows:
1. The SCI synchronizes with serial clock input or output and initializes internally.
2. Receive data is stored into the SCRSR in order from the LSB to the MSB. After receiving the
3. After setting RDRF to 1, if the RIE is set to 1 in the SCSCR, the SCI requests a receive-data-
Figure 14.22 shows an example of the SCI receive operation.
Rev. 4.00, 03/04, page 394 of 660
data, the SCI checks that RDRF is 0 so that receive data can be loaded from the SCRSR into
the SCRDR. If this check is passed, the SCI sets RDRF to 1 and stores the received data in the
SCRDR. If the check is not passed (receive error), the SCI operates as indicated in table 14.11.
This state prevents further transmission or reception. While receiving, the RDRF bit is not set
to 1. Be sure to clear the error flag.
full interrupt (RXI). If the ORER bit is set to 1 and the RIE in the SCSCR is also set to 1, the
SCI requests a receive-error interrupt (ERI).
Synchronization
ORER
RDRF
Serial
clock
data
RXI interrupt
generated
request
Transfer direction
Figure 14.22 Example of SCI Receive Operation
Bit 7
Bit 0
processing routine
and clears RDRF
the RXI interrupt
Reads data with
1 frame
bit to 0
Bit 7
Bit 0
RXI interrupt
generated
request
Bit 1
request generated
by overrun error
Bit 6
ERI interrupt
Bit 7