HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 227

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HD6417706

Manufacturer Part Number
HD6417706
Description
Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Bit
15
14
13
12
Bit Name
TPC1
TPC0
RCD1
RCD0
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
RAS Precharge Time
When synchronous DRAM interface is selected as
connected memory, they set the minimum number
of cycles until output of the next bank-active
command after precharge.
The number of cycles to be inserted immediately
after issuing a precharge all banks (PALL)
command in auto-refresh or a precharge (PRE)
command in bank-active mode is one cycle less
than the normal value. In bank-active mode,
neither TPC1 nor TPC0 should be cleared to 0.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
Note: * Immediately after a precharge all banks (PALL)
RAS-CAS Delay
When synchronous DRAM interface is selected as
connected memory, sets the bank active
read/write command delay time.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
Normal
Operation
command in auto-refresh and a precharge (PRE)
command in bank-active mode.
Rev. 4.00, 03/04, page 181 of 660
Immediately after* Immediately
Precharge
Command
0 cycle
1 cycle
2 cycles
3 cycles
after
Self-Refresh
2 cycles
5 cycles
8 cycles
11 cycles

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