HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 341

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Mode 0: An external clock is input from the EXTAL pin and undergoes waveform shaping by
PLL circuit 2 before being supplied inside this LSI. The frequency ratio between EXTAL input
clock and CKIO output clock is 1:1. An input clock frequency of 25 MHz to 66.67 MHz can be
used, and the CKIO frequency range is 25 MHz to 66.67 MHz.
Mode 1: An external clock is input from the EXTAL pin and its frequency is multiplied by 4 by
PLL circuit 2 before being supplied inside this LSI, allowing a low-frequency external clock to be
used. The frequency ratio between EXTAL input clock and CKIO output clock is 1:4. An input
clock frequency of 6.25 MHz to 16.67 MHz can be used, and the CKIO frequency range is 25
MHz to 66.67 MHz.
Mode 2: The on-chip crystal oscillator operates, with the oscillation frequency being multiplied by
4 by PLL circuit 2 before being supplied inside this LSI, allowing a low crystal frequency to be
used. The frequency ratio between crystal oscillation and CKIO output clock is 1:4. A crystal
oscillation frequency of 6.25 MHz to 16.67 MHz can be used, and the CKIO frequency range is 25
MHz to 66.67 MHz.
Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and
undergoes waveform shaping, and also frequency multiplication according to the setting, by PLL
circuit 1 before being supplied to this LSI. In modes 0 to 2, the system clock is generated from the
output of this LSI's CKIO pin. Consequently, if a large number of Ics are operating synchronized
with the clock, the CKIO pin load will be large. This mode, however, assumes a comparatively
large-scale system. If a large number of ICs are operating on the clock cycle, a clock generator
with a number of low-skew clock outputs can be provided, so that the ICs can operate
synchronously by distributing the clocks to each one.
As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for
connection of synchronous DRAM.
Rev. 4.00, 03/04, page 295 of 660