HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 339

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The clock pulse generator blocks function as follows:
1. PLL Circuit 1: PLL circuit 1 doubles, triples, quadruples, or leaves unchanged the input clock
2. PLL Circuit 2: PLL circuit 2 leaves unchanged or quadruples the frequency of the crystal
3. Crystal Oscillator: This oscillator is used when a crystal oscillator element is connected to the
4. Divider 1: Divider 1 generates a clock at the operating frequency used by the internal clock.
5. Divider 2: Divider 2 generates a clock at the operating frequency used by the bus clock (B )
6. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock
7. Standby Control Circuit: The standby control circuit controls the state of the clock pulse
8. Frequency Control Register: The frequency control register has control bits assigned for the
9. Standby Control Register: The standby control register has bits for controlling the power-down
frequency from the CKIO terminal. The multiplication rate is set by the frequency control
register. When this is done, the phase of the leading edge of the internal clock (I , B , P ) is
controlled so that it will agree with the phase of the leading edge of the CKIO pin.
oscillator or the input clock frequency coming from the EXTAL pin. The multiplication ratio is
fixed by the clock operation mode. The clock operation mode is set by pins MD0, MD1, and
MD2. See table 10.3 for more information on clock operation modes.
XTAL and EXTAL pins. It operates according to the clock operating mode setting.
The operating frequency can be 1, 1/2, 1/3, or 1/4 times the output frequency of PLL circuit 1,
as long as it stays at or above the clock frequency of the CKIO pin. The division ratio is set in
the frequency control register.
and peripheral clock (P ). The operating frequency of the peripheral clock can be 1, 1/2, 1/3,
1/4, or 1/6 times the output frequency of PLL Circuit 1, as long as it stays at or below the clock
frequency of the CKIO pin. The division ratio is set in the frequency control register.
frequency using the MD2 to MD0 pins and the frequency control register.
generator and other modules during clock switching and sleep/standby modes.
following functions: clock output/non-output from the CKIO pin, on/off control of PLL circuit
1, PLL standby, the frequency multiplication ratio of PLL 1, and the frequency division ratio
of the internal clock and the peripheral clock.
modes. See section 22, Power-Down Modes, for more information.
Rev. 4.00, 03/04, page 293 of 660